1. Field of the Invention
This invention relates to a reload timer circuit, and more particularly, to a reload timer circuit by which a reload value is rewritten to thereby gradually change a period of an n-bit timer signal.
2. Description of the Related Art
Due to the demand for an improved control technology, for increasing the speed and efficiency of microcomputers, many functions carried out so far by software are being gradually replaced with hardware.
As an example, a conventional reload timer circuit serving as a peripheral circuit of a microcomputer will be explained. The reload timer circuit changes a reload value to thereby gradually change the period of a timer signal, and to rewrite the reload value of the reload timer circuit, a central processing unit (CPU) must issue an interrupt request, which causes an overload of the CPU software and hinders the execution of other programs.
An operation of a typical conventional reload timer circuit will be explained with reference to FIG. 1.
In the figure, the reload timer circuit for providing a timer signal having a period which is gradually changed comprises a 4-bit reload register circuit 1 and a 4-bit timer circuit 2. The 4-bit reload register circuit 1 includes four flip-flops FR21 to FR24 connected to a bus 4. The 4-bit timer circuit 2 includes four flip-flops FT21 to FT24.
The 4-bit reload register circuit 1 receives input data of four bits D0 to D3 from a CPU 3 in response to a first write signal WR12, and provides the 4-bit timer circuit 2 with reload data of four bits QC00 to QC13 in response to a second write signal WR22 provided by and AND gate in accordance with a count clock signal CK22 provides timer data of four bits QT0 to QT3 in responses to the count clock signal CK22.
Thereafter, the CPU 3 provides, based on the first write signal WR12, the flip-flops FR21 to FR24 of the 4-bit reload register circuit 1 with the next input data of four bits D0' to D3' that are different from the data D0 to D3 stored in the 4-bit reload register circuit 1. The new data D0' to D3' are transferred from the reload register circuit 1 to the timer circuit 2 when the second write signal WR22 again rises, and the timer circuit 2 then carries out a counting operation at a timer period defined by the new data D0' to D3' and different from that defined by the previous data D0 to D3.
By repeating the above process and by utilizing software, the reload timer circuit provides gradually changes a period of a timer signal.
Namely, the CPU 3 relies on a software program to rewrite the reload data QC00 to QC13, to thus gradually change the timer period, and this technique overloads the CPU 3 and hinders the execution of other programs.
FIG. 2(a) is a characteristic diagram showing a D/A conversion process carried out through, for example, a pulse width modulator (PWM), wherein after receiving a level conversion request, the CPU 3 controls the PWM to smoothly shift a level from L1 to L2.
The level is shifted from L1 to L2 by controlling a high level width ratio of a timer signal to a low level. For example, the low level width of the timer signal is fixed, and the high level width of the signal is changed according to the period of the timer signal.
This will be explained in more detail with reference to FIG. 2(b). In a state (1) at the level L1, the CPU 3 writes, according to a program, a reload value of, for example, 0101 in the 4-bit reload register circuit 1, so that the 4-bit timer circuit 2 can count down from 5 to 0 to reach a state (2). When the count reaches 0, the CPU 3 write the next reload value of, for example, 0110 in the register circuit 1, so that the timer circuit 2 can count down from 6 to 0 to reach a state (3). This operation is repeated to gradually extend the period of the timer circuit 2 until a state (4) is attained.
Accordingly, the conventional technique changes the level of an analog value from L1 to L2 by executing a CPU program in such a way as to change input data stored in the reload register circuit 1 at a predetermined timing (in the above example, the input data is incremented), to thereby change the period of the timer circuit 2.
According to this example, an ON duty ratio of an output signal of the timer circuit 2 is increased, and a voltage or each period is averaged by, for example, an integration circuit, to thereby provide a voltage value corresponding to the timer period. This technique, however, must change data at each of the predetermined timings (1) to (4). In addition, to smoothly shift the level, the CPU 3 must change the data more frequently, and this may lower the efficiency. Whenever the states (1) to (4) are changed from one state to the next, the CPU 3 must terminate other program executions and issue an interrupt request to rewrite a reload value for the timer circuit 2. This may overload the CPU 3, hinder the execution of other programs, and prevent a high-speed processing.
Therefore, it is required to provide a timer circuit provided with hardware for automatically setting a reload value, once an initial reload value is set in a register, to thereby lighten the load of the CPU software.